Reference is now made to FIG. 1 illustrating a circuit diagram for a conventional instrumentation amplifier circuit 10 as known to those skilled in the art. The circuit 10 includes a first input buffer amplifier 12 and a second input buffer amplifier 14. The amplifiers 12 and 14 are typically formed as operational amplifiers (OPAMPs). The non-inverting (+) input terminals of amplifiers 12 and 14 are configured to receive a differential input signal Vin. The inverting (−) input terminal of amplifier 12 is coupled by a feedback resistor R1 to the amplifier output terminal. Likewise, the inverting (−) input terminal of amplifier 14 is coupled by a feedback resistor R1 to the amplifier output terminal. A resistor R2 is coupled between the inverting (−) input terminal of amplifier 12 and the inverting (−) input terminal of amplifier 14. A differential output signal Vout is generated at the output terminals of the amplifiers 12 and 14. The gain (G) of the amplifier circuit 10 is given by the following equation: G=1+(2*R1/R2).
The amplifier circuit 10 may be used as a fixed gain amplifier (FGA) by setting the values of R1 and R2 in order to achieve a desired gain G. Alternatively, the amplifier circuit 10 may be used as a variable gain amplifier (VGA) or programmable gain amplifier (PGA) by adjusting the values of R1 and R2. In a preferred implementation, the resistor R2 is provided as a variable resistor to control the amplifier gain G using changes made to a single resistor.
FIG. 2 illustrates a conventional signal processing path 20 including a fixed gain amplifier (FGA) 22 configured to receive a differential input signal 24 and output a first differential output signal 26 with a fixed gain Gf. The path 20 further includes a programmable gain amplifier (PGA) 28 configured to receive the first differential output signal 26 and output a second differential output signal 30 with a programmable gain Gp. The second differential output signal 30 is then converted by an analog-to-digital converter (ADC) 32 to generate a digital output signal 34. The path 20 further includes a gain register (or other control circuit) 36 coupled to the programmable gain amplifier 28. The data value loaded into the gain register 36 sets the programmable gain Gp.
FIG. 3 illustrates a conventional signal processing path 20′ including a fixed gain amplifier (FGA) 22′ configured to receive a differential input signal 24′ and output a first differential output signal 26′ with a fixed gain Gf. The path 20′ further includes an analog modulator of a ΔΣ type including a modulator 28′ with a programmable gain amplification (PGA) functionality generating a signal 30′ with a programmable gain Gp. The signal 30′ is then filtered by a filter 32′ to generate a digital output signal 34′. The path 20′ further includes a gain register (or other control circuit) 36′ coupled to the programmable gain amplification functionality of the modulator 28′. The data value loaded into the gain register 36′ sets the programmable gain Gp.
The paths 20 and 20′ advantageously function to gain up the input analog signal 24/24′ prior to digitization. It is recognized that the input analog signal 24/24′ may be output from a source (such as a sensor) having different signal sensitivities. To maximize system signal-to-noise ratio (SNR), it is important to gain up the different input signals proportionally such that about the same analog signal amplitude is present, regardless of signal source, at the input of the analog-to-digital conversion phase. Those skilled in the art further understand that the gain settings (Gf and Gp) should preferably be greater than unity and that when multiple gain up stages are present the higher gain settings should process the signal first. Thus, it is preferred to use a relatively higher fixed gain Gf at the first gain up stage.
With respect to an analog-to-digital conversion referenced to a reference voltage Vref, the input full-scale-range (FSR) is given by the following equation: FSR=Vref/(Gf*Gp). In this context, the FSR is the maximum input signal that is allowed by the path 20/20′ without incurring output code saturation at the analog-to-digital converter. Thus, the optimal setting of the fixed gain Gf for a given signal source is the gain at which the maximum expected analog output signal (prior to conversion) is close to without exceeding the reference voltage Vref.
The fixed gain amplifier (FGA) 22/22′ in FIGS. 2 and 3 may, for example, comprise the instrumentation amplifier circuit 10 of FIG. 1 with the resistors R1 and R2 set to achieve the desired fixed gain Gf in accordance with the following equation: Gf=1+(2*R1/R2). The differential input signal 24/24′ has a common mode voltage Vcm>0, and thus the first differential output signal 26/26′ will have a corresponding common mode voltage Vcm. The common mode voltage must be set at a value which ensures that the differential output signal 26/26′ is not clipped (i.e., goes too negative or too positive towards the supply rails for the amplifiers 12 and 14 to handle). With the analog-to-digital conversion referenced to a reference voltage Vref, the maximum output for the first differential output signal 26/26′ must be less than or equal to Vref/Gp so as to ensure the analog-to-digital conversion is not saturated.
Increasing the programmable gain Gp value to provide sufficient amplification prior to analog-to-digital conversion with respect to a smaller magnitude differential input signal 24/24′ raises a power dissipation concern. The power dissipation in the fixed gain amplifier is a function of the current flowing through the resistors R1 and R2 as well as the static (quiescent) current of the OPAMPs. The current flowing through the resistors is inversely proportional to programmable amplifier gain. Additionally, output swing changes with change in the programmable gain Gp value. When the programmable gain Gp value decreases, output swing increases. This means that there is more power dissipation in the fixed gain amplifier for lower programmable gain Gp values than for higher programmable gain Gp values. A need thus exists to address the dissipated power of the path 20/20′ as the programmable gain Gp value is changed.